1 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register april 1999 1999 integrated device technology, inc. dsc-4594/1 c idt74lvc646a extended commercial temperature range description the lvc646a device consists of bus-transceiver circuits, d-type flip- flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. data on the a or b bus is clocked into the registers on the low-to-high transition of the appropriate clock (clkab or clkba) input. output-enable ( oe ) and direction-control (dir) inputs control the transceiver functions. in the transceiver mode, data present at the high- impedance port is stored in either register or in both. the select-control (sab and sba) inputs can multiplex stored and real-time (transparent mode) data. dir determines which bus receives data when oe is low. in the isolation mode ( oe high), a data is stored in one register and b data can be stored in the other register. when an output function is disabled, the input function is still enabled and can be used to store and transmit data. only one of the two buses, a or b, can be driven at a time. the lvc646a has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. inputs can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v system environ- ment. features: C 0.5 micron cmos technology C esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) C 1.27mm pitch soic, 0.65mm pitch ssop, 0.635mm pitch qsop, 0.65mm pitch tssop packages C extended commercial range of C 40c to +85c Cv cc = 3.3v 0.3v, normal range Cv cc = 2.3v to 3.6v, extended range C cmos power levels (0.4 w typ. static) C rail-to-rail output swing for increased noise margin C all inputs, outputs and i/o are 5 volt tolerant C supports hot insertion 3.3v cmos octal bus transceiver and register with 3-state outputs and 5 volt tolerant i/o functional block diagram to seven other channels b 1 1 d c 1 1 d c 1 a 1 sab clkab sba oe clkba 21 23 22 1 2 4 20 dir 3 one of eight channels drive features for lvc646a: C high output drivers: 24ma C reduced system switching noise applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems
2 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register soic/ ssop/ qsop/ tssop top view pin configuration absolute maximum ratings (1) symbol description max. unit v term (2) terminal voltage with respect to gnd C 0.5 to +6.5 v v term (3) terminal voltage with respect to gnd C 0.5 to +6.5 v t stg storage temperature C 65 to +150 c i out dc output current C 50 to +50 ma i ik i ok continuous clamp current, v i < 0 or v o < 0 C 50 ma i cc i ss continuous current through each v cc or gnd 100 ma 8lvc notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliab ility. 2. v cc terminals. 3. all terminals except v cc . capacitance (t a = +25c, f = 1.0mh z ) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf 8lvc lin k note: 1. as applicable to the device type. 2 3 1v cc 20 19 18 b 2 b 1 b 3 sba 15 a 7 16 9 10 b 4 23 22 24 21 17 5 6 a 4 7 a 2 a 3 4 a 1 so24-2 so24-7 so24-8 so24-9 8 a 5 13 clkba 14 11 12 gnd clkab sab dir a 6 a 8 oe b 5 b 6 b 7 b 8 notes: notes: notes: notes: notes: 1. h = high voltage level l = low voltage level x = dont care - = low-to-high transition 2. the data output functions may be enabled or disabled by various signals at the oe or dir inputs. data input functions are always enabled; i.e., data at the bus pins willl be stored on every low-to-high transition on the clock inputs. pin description pin names description ax data register a inputs data register b outputs bx data register b inputs data register a outputs clkab, clkba clock pulse inputs sab, sba output data source select inputs oe output-enable input dir direction-control input function table (1) inputs data i/o oe dir clkab clkba sab sba a1-a8 b1-b8 operation or function x x x x - x x - x x x x input unspecified (2) unspecified (2) input store a, b unspecified (2) store b, a unspecified (2) h h x x - h or l - h or l x x x x input input disabled input input disabled store a and b data isolation, hold storage l l l l x x x h or l x x l h output output input input real-time b data to a bus stored b data to a bus l l h h x h or l x x l h x x input input output output real time a data to b bus stored a data to b bus
3 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register bus a bus b oe l dir l clkab x clkba x sab x sba l bus a bus b dir h oe l clkab x clkba x sab l sba x bus a bus b oe x x h dir x x x clkab - x - clkba x - - sab x x x sba x x x bus a bus b dir l h oe l l clkab x h or l clkba h or l x sab x h sba h x real-time transfer bus a to bus b real-time transfer bus b to bus a storage from a, b, or a and b transfer stored data to a and/or b
4 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = C 40c to +85c symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 v v cc = 2.7v to 3.6v 2 v il input low voltage level v cc = 2.3v to 2.7v 0.7 v v cc = 2.7v to 3.6v 0.8 i ih i il input leakage current v cc = 3.6v v i = 0 to 5.5v 5 a i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v 50 a v ik clamp diode voltage v cc = 2.3v, i in = C 18ma C 0.7 C 1.2 v v h input hysteresis v cc = 3.3v 100 mv i ccl i cch quiescent power supply current v cc = 3.6v v in = gnd or v cc 10a i ccz 3.6 v in 5.5v (2) 10 d i cc quiescent power supply current variation one input at v cc - 0.6v, other inputs at v cc or gnd 500 a 8lvc lin k notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = C 0.1ma v cc C 0.2 v v cc = 2.3v i oh = C 6ma 2 v cc = 2.3v i oh = C 12ma 1.7 v cc = 2.7v 2.2 v cc = 3.0v 2.4 v cc = 3.0v i oh = C 24ma 2.2 v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma 0.2 v v cc = 2.3v i ol = 6ma 0.4 i ol = 12ma 0.7 v cc = 2.7v i ol = 12ma 0.4 v cc = 3.0v i ol = 24ma 0.55 8lvc link note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriate v cc range. t a = C 40c to +85c.
5 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation capacitance per transceiver outputs enabled c l = 0pf, f = 10mhz 75 pf c pd power dissipation capacitance per transceiver outputs disabled 9 pf switching characteristics (1) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min . max. min . max. min. max. unit f max 150 150 mhz t plh t phl propagation delay ax to bx or bx to ax 7.9 1.4 7.4 ns t plh t phl propagation delay clk to ax or bx 8.8 1.3 8.4 ns t plh t phl propagation delay sba or sab to ax or bx 9.9 1.4 8.6 ns t pzh t pzl output enable time oe to ax 10.2 1 8.2 ns t pzh t pzl output enable time dir to bx 10.4 1.2 8.3 ns t phz t plz output disable time oe to ax 8.9 1 7.5 ns t phz t plz output disable time dir to bx 8.7 1.1 7.9 ns t w pulse duration 3.3 3.3 ns t su setup time, data before clk - 1.6 1.5 ns t h hold time, data after clk - 1.7 1.7 ns t sk(o) output skew (2) 500ps notes: 1. see test circuits and waveforms. t a = C 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
6 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register open v load gnd v cc pulse generator d.u.t. 500 w 500 w c l r t v in v out (1, 2) 8lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 8lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t 8lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t 8lvc link low-high-low pulse high-low-high pulse v t t w v t 8lvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz 8lvc link test cir cuits and w a veforms test conditions propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times switch position output skew - tsk (x) pulse width symbol v cc (1) = 3.3v 0.3v v cc (1) = 2.7v v cc (2) = 2.5v 0.2v unit v load 662 x vccv v ih 2.7 2.7 vcc v v t 1.5 1.5 v cc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf 8lvc link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. note: 1. diagram shown for input control enable-low and input control disable-high. test switch open drain disable low enable low v load disable high enable high gnd all other tests open 8lvc lin k
7 extended commercial temperature range idt74lvc646a 3.3v cmos octal bus transceiver and register corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information idt xx lvc xxxx xx package device type temp. range so py q pg 74 small outline ic (gull wing) (so24-2) shrink small outline package (so24-7) quarter size small outline package (so24-8) thin shrink small outline package (so24-9) octal bus transceiver and register with 3-state outputs, 24ma C40c to +85c x bus-hold 646a no bus-hold blank
|
